1. Field of the Invention
The present invention relates to an instruction processing apparatus in an information processing system.
2. Description of the Related Art
In an information processing system, when a load control (LCTL) instruction or other instruction requiring serial processing, a load program status word (LPSW) instruction or other instruction for changing the controlled state of a system, or an interrupt is executed, instructions have to be re-read.
Recent information processing systems use a microprogram so as to execute instructions while reducing the hardware. Similar use is made of a microprogram for realizing a method for re-reading instructions due to execution of an LCTL instruction or other instruction requiring serial processing, a LPSW instruction or other instruction for changing the controlled state of a system, or an interrupt.
FIG. 1 is a flowchart of the routine for an instruction re-read operation using a microprogram.
An instruction re-read operation using a microprogram is realized by, in time, starting up the microprogram (step S1), halting the reading of instructions (step S2), setting an instruction read address (step S3), and starting the reading of instructions (step S4).
A conventional instruction processing unit adopting pipeline processing performs similar processing to that of FIG. 1.
A conventional instruction re-read method using pipeline processing will be described next using FIG. 2 to FIG. 13. FIG. 2 to FIG. 5 show an instruction processing circuit. FIG. 2 shows the overall configuration of the circuit and the connection of FIG. 3 to FIG. 5. FIG. 6 to FIG. 8 are timing charts of instruction re-re-read processing. FIG. 9 to FIG. 13 show the hardware configuration employed in the instruction processing circuit.
A basic instruction re-read operation description follows.
The basic instruction re-read processing is performed by an LPSW instruction. Among the timing charts of FIG. 6 to FIG. 8, FIG. 6 shows the processing of this example.
The routine of FIG. 1 in an LPSW instruction as executed as follows. First, in the startup of the microprogram of step S1 of FIG. 1, instructions fetched into an instruction buffer (IBUFFER) of FIG. 3 are loaded into an instruction register (IWR), the instructions are decoded at the D-cycle, and an operation code (IO) is supplied to a control storage address register (CSAR). By this, microprogram control information (PLHC, PCR, LAST-WORD, etc.) is successively read from a main control storage (MCS) into a D-tag (DTAG). The PLHC is a Pipeline Hardware Control used for interlock controlling of the pipeline, the PCR is a Program Control Register mainly used for controlling REGISTER, and the LAST-WORD (Last-Word) contains data read from the MCS, which shows the end of the microprogram. The microprogram control information is shifted from the D-cycle to a W-Cycle for the processing at the cycles (D-Cycle to W-Cycle).
The halting of the reading of instructions at step S2 of FIG. 1 is performed by a function counter 2 (FC2) of FIG. 6. Microprogram control information (PLHC=0C) of the FC2 read from the MCS of FIG. 3 is shifted from the D-cycle to the W-cycle. At this time, the microprogram control information (PLHC=0C) from the TTAG of the T-cycle is decoded and a T-CONTROL signal (A) is produced (see FIG. 10) and sent to an instruction reading control unit of FIG. 3. For explanation, a function counter (e.g. FC2, shown in FIG. 6) indicates a count of a series of processes from D-cycle to W-cycle. The function counters FC0-FCn are not constituted by hardware, but are indications that show function units processed by the data read from the MCS in each fetch cycle.
The sent T-CONTROL signal (A) activates the RE-IFCH-TGR of FIG. 12 and halts the reading of instructions by a signal (C): +IF-REQ signal sent from the instruction reading control unit of FIG. 3 (see FIG. 12). At the same time, the instruction buffer is initialized by clearing the NSI-COUNTER of FIG. 3 showing the state of the IBUFFER and the location of instructions by a signal (D): xe2x88x92INITIALIZE-NSIC signal (see FIG. 12) sent from the instruction reading control unit.
The setting of the instruction read address of step S3 in FIG. 1 is performed by a function counter FC0 of FIG. 6. The microprogram control information (PCR=14) of the FC0 read from the MCS of FIG. 3 is shifted from the D-cycle to the W-cycle. At this time, an operand fetch instruction is issued by an A-CONTROL signal of the A-cycle of FIG. 4, microprogram control information (PCR=14) is decoded from the WTAG of the W-cycle of FIG. 5, a W-CONTROL signal (E) is produced (see FIG. 11), the result register latch (RR-LCH) of FIG. 5 is selected, and the output is written in a program status word (PSW).
Next, at the W+1 cycle of FIG. 5, an instruction address (PSWIAR) of the PSW updated by a W-CONTROL-LCH signal (F) latching the W-CONTROL signal (E) of FIG. 11 is loaded into an instruction address register (IAR).
The starting of reading of instructions of step S4 of FIG. 1 is performed by FC5 of FIG. 6. Microprogram control information (LAST-WORD) of the FC5 read from the MCS of FIG. 3 is shifted from the D-cycle to the W-cycle. At this time, the AND of the microprogram control information (LAST-WORD) and a D-VALID signal (signal indicating that the D-cycle is valid) is taken from the DTAG of the D-cycle of FIG. 3, whereby an NSI-REQ signal (G) is produced and sent to the instruction reading control unit of FIG. 3.
The NSI-REQ signal (G) sent to the instruction reading control unit of FIG. 3 resets the latch of RE-IFCH-TRG of FIG. 12 and then activates the latch of START-UP, whereby an IF-REQ signal (C) is sent from the next clock cycle and thereby instructions start being read.
By the processing of the microprogram as explained above, the routine of FIG. 1 is satisfied and the basic instruction re-read operation indicated in FIG. 6 is carried out.
An example of producing subsequent instruction address and performing instruction re-read operation follows. The instruction re-read operation at the subsequent instruction address is performed by the load control (LCTL) instruction. Among the timing charts of FIG. 6 to FIG. 8, FIG. 7 shows the processing of this example.
The LCTL also performs the instruction re-read operation according to the routine of FIG. 1. The startup of the microprogram for the instruction re-read operation of step S1, the halting of reading of instructions of step S2, and the starting of reading of instructions of step S4 in this example are similar to those of the above explanation of the basic instruction re-reading operation. Only the setting of the instruction read address of step S3 differs.
In the same way as the above basic instruction re-reading operation, a microprogram is started up at step S1 and the halting of the reading of instructions of step S2 is performed by the FC2 of FIG. 7.
The setting of the instruction read address of step S3 of FIG. 1 is performed by the FC6 of FIG. 7. In the same way as the microprogram control information (PLHC=0F) of the FC6 read from the MCS of FIG. 3 being shifted from the D-cycle to the W-cycle, an address in the IAR corrected by an instruction address modifier (IAM) sent from the instruction reading control unit of FIG. 3 and an instruction length code decoded from the IWR are shifted.
At this time, microprogram control information (PLHC=0F) is decoded from the TTAG of the T-cycle, a T-CONTROL signal (B) is produced (see FIG. 10), TIAR+TILC obtained by adding the data of the T-cycle instruction address register (TIAR) and the T-cycle of FIG. 4 instruction length code (TILC) is selected, and the TIAR+TILC is loaded into the IAR.
Next, for the start of the reading of instructions of step S4 of FIG. 1, processing similar to that explained in the above basic instruction re-read operation is performed by the FC8.
By the processing of the microprogram as explained above, the routine of FIG. 1 is satisfied and the basic instruction re-read operation indicated in FIG. 7 is carried out.
An Example of Performing Instruction Re-read Operation Influenced by State of CPU in Interrupt Processing follows.
Among the timing charts of FIG. 6 to FIG. 8, FIG. 8 shows the processing of this example.
In the instruction re-reading operation influenced by the state of the CPU in the interrupt processing, an instruction re-read operation is performed according to the routine of FIG. 1. The startup of the microprogram for the instruction re-read operation of step S1, the halting of reading of instructions of step S2, and the setting of the instruction read address of step S3 in this example are similar to those of the above explanation of the basic instruction re-reading operation. Only the starting of reading of instructions of step S4 differs.
In the same way as the above basic instruction re-reading operation, a microprogram is started up at step S1, the halting of the reading of instructions of step S2 is performed by the FC2 of FIG. 8, and the setting of the instruction read address of step S3 is performed by the FC0.
The starting of the reading of instructions of step S4 of FIG. 1 is performed by the FC8 of FIG. 8. Microprogram control information (LAST-WORD) of the FC8 read from the MCS is shifted from the D-cycle to the W-Cycle. At this time, the AND of the microprogram control information (LAST-WORD) and D-VALID signal (signal indicating that the D-cycle is valid) is taken from the DTAG of the D-cycle, whereby an NSI-REQ signal (G) is produced (see FIG. 9) and sent to the instruction reading control unit and process control unit of FIG. 3.
The NSI-REQ sent to the instruction reading control unit of FIG. 3 resets the latch of RE-IFCH-TGR of FIG. 12 and activates the latch of START-UP. The NSI-REQ sent to the process control unit of FIG. 3 is latched and the AND of the latched signal and an END-PROCESS-STATE signal (see FIG. 13) is taken, whereby the state is changed from a START state to a PROCESS state. When the PROCESS state is entered, the Enable Process Instruction Fetch (ENB-PROCESS-IFCH) of FIG. 12 is activated, whereby the IF-RED signal (C) is sent from the next clock cycle and thereby instructions start being read. The ENB-PROCESS-IFCH indicates that the instruction fetch process is valid.
By the processing of the microprogram as explained above, the routine of FIG. 1 is satisfied and the basic instruction re-read operation indicated in FIG. 8 is carried out.
The conventional instruction re-read method using pipeline processing explained above, however, suffered from the following three problems:
1. Calculation of Subsequent Instruction Address
In the conventional pipeline type instruction processing method, the subsequent instruction address is calculated by the T-cycle instruction address register and T-cycle instruction length code. Doing this invites an increase in the hardware, so a new method of calculating a subsequent instruction address is needed.
2. Starting of Reading of Instructions
The conventional operation for starting reading of instructions, as indicated in FIG. 6 to FIG. 8, starts the subsequent reading of instructions by the NSI-REQ signal at the D-cycle of the last cycle of the microprogram. This is due to the fact that, in the conventional control for loading instructions, as shown in FIG. 3, the initial instruction fetch data is loaded directly to the IWR without passing through the IBUFFER, therefore if reading of subsequent instructions is started during execution of a current instruction at the time of an instruction re-read operation, the content of the IWR may be destroyed.
As opposed to this, the content of the IWR will never be destroyed when the reading of subsequent instructions is started, in the D-cycle of the last cycle of a microprogram, as shown in FIG. 6 to FIG. 8. However, when the reading of instructions is started at the D-cycle of the last cycle, if the number of clock cycles for the processing for reading instructions increases due to cache errors in instruction fetching operations, conversion of instruction address, etc., the loading of instructions to the instruction execution control unit is delayed by the amount of the increase in the number of clock cycles caused by the processing for reading the instructions.
3. State Transition of CPU
In interrupt processing, starting from the D-cycle of the last cycle, the state changes from the ENDPROCESS-STATE to START and to PROCESS-STATE. The reading of instructions is first started at PROCESS-STATE. Therefore, the reading of subsequent instructions is delayed.
An object of the present invention is to establish a new method of re-reading instructions and to increase the instruction re-reading speed in an instruction re-read operation using a microprogram while decreasing the hardware. In the present invention, along with changes in the method of executing instructions, there is provided an instruction re-read operation using a microprogram which can establish a new method of rereading instructions and realize an increase in speed of the instruction re-read operationxe2x80x94a perennial problem in information processing systemsxe2x80x94while reducing the hardware.
The present invention was made to achieve the above object.
The instruction processing apparatus according to the present invention provides a queue stack to execute instructions. Moreover, it employs a method under which all control for loading instructions goes through an instruction buffer (IBUFFER) and instructions are loaded into an instruction register (IWR). Due to this, it is possible to avoid the case of destruction of the content of the IWR by simple control (this is explained in the discussion below of FIGS. 33 to 35, which precedes the explanation of the overall instruction re-read operation of FIG. 20). In the processing of the microprogram for the instruction re-read operation, by performing the instruction fetching operation in advance during the execution of the microprogram, it becomes possible to load instructions in the instruction execution pipeline soon after the completion of the processing of the microprogram.
The present invention is further provided with the later explained means for the following reasons:
1. In an instruction processing apparatus, an instruction execution control unit and an instruction fetch pipeline operate mutually independently, therefore microprogram processing and instruction fetch processing can be executed simultaneously.
2. There are methods of calculating subsequent instruction addresses without calculation of the T-cycle instruction address and T-cycle instruction length code.
3. The END-PROCESS STATE is required for starting a microprogram for interrupt processing etc., but while the microprogram for interrupt processing is running, the END-PROCESS-STATE is not required.
For the reasons above, the following means are provided:
1. An instruction reading request halt control register, a halt unit halting an instruction reading request issued by a microprogram, and a halt releasing unit are provided so as to enable an instruction re-read operation.
2. The start of reading instructions of FIG. 1 is instructed by separate microprogram control information so as to enable simultaneous execution of the instruction re-reading processing with the execution of a microprogram and to enable an increase of speed of the instruction re-read operation.
3. A unit holding a self instruction address and self instruction length due to microprogram instructions in an instruction re-read operation at a subsequent instruction address and an adder are provided so as to decrease the hardware and enable the instruction re-read operation.
4. A unit causing a change in state from the ENDPROCESS-STATE through the START-STATE to the PROCESS-STATE soon due to a microprogram instruction and enabling an instruction fetching operation in an instruction re-read operation at an interrupt processing etc. is provided so as to execute the instruction re-read operation.